1. Field
This disclosure relates generally to detecting an imminent read failure in a non-volatile memory array and, more specifically, to stress-based techniques for accelerating and detecting an imminent read failure in a non-volatile memory array.
2. Related Art
Hamming code, which is one of the most commonly implemented error correcting codes (ECCs), allows a single-bit error to be detected and corrected and (in the usual configuration, with an extra parity bit) double-bit errors to be detected (but not corrected). Various memory controllers are designed to support ECC. Most low-cost ECC-capable memory controllers only detect and correct single-bit errors of a word, e.g., a 64-bit word, and detect (but not correct) errors of two bits per word. For example, an ECC word checkbase for a 64-bit word may include seventy-two bits (i.e., sixty-four data bits and eight parity bits). Other ECC-capable memory controllers are capable of detecting and correcting multiple bits per word.
ECC has been employed in non-volatile memory (NVM) applications. For example, embedded NVM (eNVM) employed in automotive applications has implemented ECC to correct read failures. In general, a read failure occurs when what was programmed into a cell (data or code) is not read out of the cell. For example, in a typical NVM (e.g., a Flash memory) a digital one and a digital zero in a cell are indicated by a different charge. As one example, a cell that is charged may indicate a digital zero and a cell that is not charged may indicate a digital one. An NVM cell can gain or lose electrons if the cell is defective. In a typical NVM, a cell error is a hard error. That is, in a typical NVM, a cell that gains electrons will not subsequently lose electrons. Similarly, in a typical NVM, a cell that loses electrons will not subsequently gain electrons.